Characteristics in 3D Last
updated on
3 dimensional information flows ...; Approx. 12 characteristics are available to read; Also see: IC logical functions; Materials AND circuits; Transistor;
0 zero to W vs. [Base p, Characteristics = Line in slope for nb; Collector n, Characteristics = Curve for Pc; Emitter n+, Characteristics = Curve for Pe, ... ]; Also known as BJT dynamic behavior;
Cell threshold voltage in V vs. [population: qubit]; Characteristics = Multi-level cells' states in signal pattern; Note: Find your own vector;
Design rules in µm vs. [Capacitance Cground, Capacitance Ctotal, Capacitance Cx, Capacitancep-p]; Characteristics = [Line in slope; Curve; Straight line];
Input voltage Vin in V vs. [Output voltage Vout, Drain Current mA]; Characteristics = Mesh surface;
Input voltage Vin in V vs. Output voltage Vout among [PH-NL, PM-NM, PL-NH, ... ]; Characteristics = Parallel lines in non-XY coordinate;
Power dissipation in mW by gate vs. Delay in ns by each gate of [BiCMOS, CMOS, ECL, TTL, ... ]; Characteristics = Parallel lines in slope;
Power supply voltage VDD in V vs. [Normalized delay in integer quantity, Normalized power dissipation in integer quantity, ... ]; Characteristics = Consecutive lines in slope and curve;
Time in ns vs. [A, B, Carry IN, Carry OUT, SUM]; Characteristics = Signal's pattern; Full adder simulation;
Time in ns vs. CLK, clock [Data Out, DDR, ... ]; Characteristics = Synchronous pattern;
Time in ns vs. quantitative DFF, D type flip-flop [CK, CK bar, D, Qm, Qs]; Characteristics = DFF transient I/O signal pattern;
Time in ns vs. [Last adder stage Carry IN, SUM (1), SUM (2), SUM (3), SUM (4), SUM (5), SUM (6), SUM (7), SUM (LSB), SUM (MSB)]; Characteristics = Signal's pattern in propagation; 8 bit carry ripple adder;
Time in s [any given time] vs. Clock of [CLK, CLK, ... ]; Characteristics = Clock skew pattern as variation;
|
|
|
 |
|
